Sliced Coordinate List Implementation Analysis on Sparse Matrix-Vector Multiplication Using Compute Unified Device Architecture

Sparse Matrix-Vector Multiplication FPGA Implementation

Sparse Matrix-Vector Multiplication using Pthreads

Optimizations: 1) Loop Optimization [1]: A typical matrix-vector multiplication (matrix in CSR format) consists of a nested loop where the outer loop iterates over all the rows and the inner loop iterates over columns in those rows. Since the data is stored in a sequential fashion in CSR (one row after the other), the data can be accessed by the nested loop using a single loop variable instead ...

Sparse Matrix-Vector Multiplication using FPGA

The Sliced COO Format for Sparse Matrix-Vector Multiplication on CUDA-enabled GPUs

Existing formats for SparseMatrix-Vector Multiplication (SpMV) on the GPU are outperforming their corresponding implementations on multi-core CPUs. In this paper, we present a new format called Sliced COO (SCOO) and an efficient CUDA implementation to perform SpMV on the GPU. While previous work shows experiments on small to medium-sized sparse matrices, we perform evaluations on large sparse m...

Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs

executing memory-intensive simulations, such as those required for sparse matrix-vector multiplication. This effect is due to the memory bottleneck that is encountered with large arrays that must be stored in dynamic RAM. An FPGA core designed for a target performance that does not unnecessarily exceed the memory imposed bottleneck can be distributed, along with multiple memory interfaces, into...